Guidelines for the power constrained design of a CMOS tuned LNA

Abstract

The first stage of a receiver is typically an LNA (low noise amplifier) which must provide sufficient gain while introducing as little noise as possible. Recently proposed noise optimization techniques for CMOS RF circuits permit greater flexibility in selection of device geometries as well as matching elements and biasing conditions to minimize the noise figure for a specified gain or power dissipation (Shaeffer and Lee, 1997). Nevertheless, such approaches still have ambiguity because intrinsic noise is assumed to be bias-independent. To utilize the new degrees of freedom in noise figure optimization, more complete intrinsic noise information on MOSFETs across the entire bias range is needed. A recent study has reported extensive experimental noise results of the 0.75 /spl mu/m SOI MOSFET technology (Dambrine et al, 1999) but provided limited guidance for actual LNA design. A physical noise simulator has been developed using two-dimensional device simulation; successful noise simulation results have been reported for MOSFETs with channel lengths down to 0.25 /spl mu/m for the first time (Goo et al, Proc. Symp. VLSI Tech., p. 153, 1999). Based on intrinsic high frequency noise simulation results, this paper presents explicit design guidelines for a CMOS tuned LNA with power constraints.