A 6 nsec CMOS EPLD with μW standby power

1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI:10.1109/CICC.1989.56689

M. J. Allen

引用次数: 0

Abstract

A description is presented of a 28-pin CMOS EPROM (erasable programmable read-only memory)-based programmable logic device optimized for memory-address-decoding applications. A novel architecture provides high-speed operation at CMOS power levels. Reprogrammability and 100% testability of EPROM technology are added benefits. Active power is less than 25% of slower bipolar solutions, and die area is 74 mil2

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一个6nsec CMOS EPLD，带μW备用电源

介绍了一种基于28针CMOS EPROM(可擦除可编程只读存储器)的可编程逻辑器件，该器件对存储器地址解码应用进行了优化。一种新颖的架构提供了CMOS功率水平下的高速操作。EPROM技术的可重编程性和100%可测试性是额外的好处。有功功率小于慢双极解决方案的25%，且模具面积为74毫米

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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1989 Proceedings of the IEEE Custom Integrated Circuits Conference

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