Hybrid low-k/Cu dual damascene process for 45-32 nm technology node using self-assembled porous-silica ultra low-k films

Abstract

Self-assembled porous-silica ultra low-k films (k=2.1) were integrated for 45-32 nm technology node low-k/Cu dual damascene interconnects. Porosity and pore size distributions of the low-k film were controlled by controlling the concentration of the surfactant so that a tight distribution of dielectric constant was achieved. Self-assembled porous silica low-k/Cu damascene interconnects were successfully formed by developing dry etching, low pressure CMP, post CMP cleaning, Cu electroplating solution as well as a TMCTS process recovery treatment. The feasibility of low-k/Cu damascene was confirmed. Electrical characteristics showed a potential capability of the self-assembled porous-silica low-k film for the 45-32 nm technology node.