Honeywell radiation hardened 32-bit processor central processing unit, floating point processor, and cache memory dose rate and single event effects test results
G. Brown, L. Hoffmann, S.C. Leavy, J.A. Mogensen, J. Brichacek
{"title":"Honeywell radiation hardened 32-bit processor central processing unit, floating point processor, and cache memory dose rate and single event effects test results","authors":"G. Brown, L. Hoffmann, S.C. Leavy, J.A. Mogensen, J. Brichacek","doi":"10.1109/REDW.1997.629808","DOIUrl":null,"url":null,"abstract":"We will present single event effects and dose rate test results for the Honeywell Radiation Hardened 32-Bit Processor Central Processing Unit, Floating Point Processor and Cache Memory. These three chip types comprise the processor core for a 32-bit radiation-hardened, fault-tolerant processor.","PeriodicalId":328522,"journal":{"name":"1997 IEEE Radiation Effects Data Workshop NSREC Snowmass 1997. Workshop Record Held in conjunction with IEEE Nuclear and Space Radiation Effects Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1997 IEEE Radiation Effects Data Workshop NSREC Snowmass 1997. Workshop Record Held in conjunction with IEEE Nuclear and Space Radiation Effects Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/REDW.1997.629808","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
We will present single event effects and dose rate test results for the Honeywell Radiation Hardened 32-Bit Processor Central Processing Unit, Floating Point Processor and Cache Memory. These three chip types comprise the processor core for a 32-bit radiation-hardened, fault-tolerant processor.