Architectural review of polynomial bases finite field multipliers over GF(2m)

Abstract

In elliptic curve cryptography (ECC), hardware architectures of finite field (FF) multipliers are frequently proposed for polynomial as well as for normal bases representations over GF(2m). Although the polynomial bases provide efficient FF multiplication as compared to normal bases, the performance of the entire elliptic cryptosystem mainly depends upon its FF multiplier. Consequently, this paper provides a comparative overview of the recent hardware architectures of FF multipliers for polynomial bases over GF(2m). This is achieved by classifying the most recent state-of-the-art research practices into three categories: bit-serial, bit-parallel and digit-serial multipliers. The comparison of multiple techniques in this article enables the designer to select a suitable multiplier according to different application requirements such as high speed/performance, constrained environments and high throughput/area applications.