{"title":"Testing of low voltage two stage operational amplifier using oscillation test methodology","authors":"M. Kaur, J. Kaur","doi":"10.1109/ICSPCOM.2015.7150685","DOIUrl":null,"url":null,"abstract":"Oscillation test methodology (OTM) has been very effective in detecting physical defects such as open, shorts and bridging defects in low-voltage CMOS VLSI analog and mixed signal circuits. This paper discusses the OTM for low voltage two-stage operational amplifier using N-well 1μm CMOS technology with high fault coverage and minimum area overhead. Five bridging faults and one open fault have been detected. Discrete practical realizations and extensive simulations based on CMOS 1μm technology parameters using PSPICE affirm that the test technique presented for MOSFET circuits ensures high fault coverage and requires a negligible area overhead.","PeriodicalId":318875,"journal":{"name":"2015 International Conference on Signal Processing and Communication (ICSC)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 International Conference on Signal Processing and Communication (ICSC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSPCOM.2015.7150685","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
Oscillation test methodology (OTM) has been very effective in detecting physical defects such as open, shorts and bridging defects in low-voltage CMOS VLSI analog and mixed signal circuits. This paper discusses the OTM for low voltage two-stage operational amplifier using N-well 1μm CMOS technology with high fault coverage and minimum area overhead. Five bridging faults and one open fault have been detected. Discrete practical realizations and extensive simulations based on CMOS 1μm technology parameters using PSPICE affirm that the test technique presented for MOSFET circuits ensures high fault coverage and requires a negligible area overhead.