ESTD: an emitter switched thyristor with a diverter

A. Bhalla, T. Chow
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引用次数: 4

Abstract

In this paper we present a 600V Emitter Switched Thyristor with a Divener (ESTD, Fig. 2), wlth a novel stnpe design, that incorporates a p-channel diverter adjacent to the floating emitter. The Emitter Switched Thyristor (EST, Fig. 1)[1,2] is a MOS-controlled thyristor that has been demonstrated to have the unique feature of gate controlled current saturation after the thyristor latches on. This current saturation feature is retained in the ESTD. which improves the maximum controllable current of the EST with a small penalty in the forward drop. During turn-off, a negative gate voltage is applied to activate the diverter, creating a p-channel that draws away part of the hole current from the p-well. The hole current flowing under the n+ source is thereby reduced, and latching of the parasitic thyristor is suppressed to higher total current levels, increasing the maximum controllable current. Since the hole current has two alternate paths, i.e. into the cathode contact and out via the diverter MOSFET (Fig. 4), the plasma is squeezed rather like in a GTO. For a linear stripe design, there is a factor of 4 maximum theoretical improvement in controllable current density for the situation of negligible p-channel resistance. The turn-on region and the diverter MOSFET occupy the same region in the device. This leads to an increased JFET resistance in series with the lateral MOSFETs, making it harder to turn the device on. Although the thyristor latching current is relatively unchanged if the floating emitter length is the same as the EST, there is a larger knee in the forward characteristic. (This problem can be alleviated by using a heavier JFET implant.) However, once the thyristor is latched, the difference in the forward drops is small. T h e simulated forward characteristics (Fig. 3) of an EST and ESTD for ~,,,=3p, .tP=0.3ps, show the knee in the ESTD characteristic, and the small increase in forward drop with respect to the EST. (These lifetime values were estimated from the measured IGBT turn-off current waveform on the same wafer, which gave a high level lifetime rn0+ T of 3.3 p.) Snubberless resistive turn-off simulations (1OOV) showed that the EST successfully turned off 200A/cm2, Pp faling at 300A/cm2 while the ESTD failed just above 700A/cm2. In these simulations, a uniform ndrift layer doping of l O " b K 3 , thickness 50p-1, p-well surface concentration of 1017cm-3, junction depth 3 p , p-base surface concentration 3 X 1017cm-3, junction depth of 3.6pm, n+ surface concentration of 1020cm-3, junction depth l p , and a oxide thickness of lOOnm was assumed. Both ESTs and ESDTs were fabricated on wafers with a 0.02Q-cm, Sopm nepi, 3R-cm n buffer on a p+ substrate. In this study, single-cell devices (300pm long stripes) were compared. These devices were fabricated with six closely spaced floating field rings leading to the main termination designed for a 600V breakdown voltage. This eliminated the need for large p+ areas under the pads connecting the source regions to the termination. The operation of a single-cell could therefore be examined without a parasitic IGBT in parallel with the main device. The measured forward characteristics (Fig. 5 ) of stripe ESTDs with a 7 p diverter gate, 4 p off-gate were compared with those of stripe ESTs with a 1 3 p on-gate, 4 p off-gate, as a function of floating emitter length ( l o p to 3 0 p ) at current densities of 400A/cm2 and 500A/cm2. The forward drop of the 2 0 p floating emitter EST is 2.33V (2.18V simulated) and that of the ESTD is 2.56V (2.23V simulated) at 400A/cm2. The triggering current density at which the main thyristor latches on is compared in the EST and ESTD (Fig. 6), and the decrease in triggering current with increasing with the increase in floating emitter length is expected from the increase in the p-well pinch resistance under the floating emitter. The maximum controllable current density for the same devices as a function of floating emitter length was compared for resistive turn-off at lOOV with V, = k 20V (Fig. 7), showing that the ESTD consistently turns off higher current densities than the EST.
带有分流器的发射极开关晶闸管
在本文中,我们提出了一种带有潜水器的600V发射极开关晶闸管(ESTD,图2),具有新颖的带状设计,在浮动发射极附近集成了p通道分流器。发射极开关晶闸管(EST,图1)[1,2]是mos控制晶闸管,已被证明具有闸控电流饱和后的独特特性。这种电流饱和特征保留在ESTD中。这提高了EST的最大可控电流,而正向降的损失很小。在关断过程中,施加负栅极电压来激活分流器,形成一个p通道,从p阱中抽出部分空穴电流。因此减少了流过n+源下的空穴电流,寄生晶闸管的锁存被抑制到更高的总电流水平,增加了最大可控电流。由于空穴电流有两个交替路径,即进入阴极触点和通过分流MOSFET输出(图4),等离子体就像在GTO中一样被挤压。对于线性条纹设计,在p通道电阻可忽略的情况下,可控电流密度的最大理论改进系数为4。导通区和分流MOSFET在器件中占据同一区域。这导致与侧mosfet串联的JFET电阻增加,使器件更难打开。当浮射极长度与EST相同时,晶闸管锁存电流相对不变,但正向特性有较大的拐点。(这个问题可以通过使用较重的JFET植入物来缓解。)然而,一旦晶闸管锁存,正向下降的差异很小。在~…=3p, . tp =0.3ps时,EST和ESTD的模拟正向特性(图3)显示了ESTD特性中的膝盖,以及相对于EST的正向下降的小幅增加(这些寿命值是根据同一晶圆上测量的IGBT关断电流波形估计的,该波形给出了3.3 p的高水平寿命rn0+ T)。无电阻关断模拟(100v)表明,EST成功关断200A/cm2, Pp在300A/cm2时下降,而ESTD在略高于700A/cm2时失败。在这些模拟中,假设均匀漂移层掺杂了lO ' ' b K 3,厚度为50p-1, p-井表面浓度为1017cm-3,结深为3p, p-碱表面浓度为3 × 1017cm-3,结深为3.6pm, n+表面浓度为1020cm-3,结深为1p,氧化物厚度为lOOnm。在p+衬底上制备了具有0.02Q-cm, Sopm nepi, 3R-cm n缓冲层的est和esdt。在这项研究中,单细胞装置(300pm长条纹)进行了比较。这些器件由六个紧密间隔的浮动场环组成,导致主端设计为600V击穿电压。这样就不需要在连接源区域和终端的焊盘下面设置大的p+区域。因此,可以在没有寄生IGBT与主装置平行的情况下检查单细胞的操作。在电流密度分别为400A/cm2和500A/cm2时,将7 p分流门、4 p关门的条形est与13 p通门、4 p关门的条形est的正向特性与浮动发射极长度(1 ~ 30 p)的函数关系(图5)进行了比较。在400A/cm2时,20 p浮动发射极EST的正向降为2.33V(模拟值为2.18V), ESTD的正向降为2.56V(模拟值为2.23V)。对比EST和ESTD中主晶闸管闭锁时的触发电流密度(图6),可以从浮动发射极下p阱箝位电阻的增加中预期触发电流随浮动发射极长度的增加而减小。在lov和V = k 20V下,比较了相同器件的最大可控电流密度与浮动发射极长度的函数关系(图7),结果表明,ESTD始终比EST关断更高的电流密度。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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