Hot-carrier degradation evolution in deep submicrometer CMOS technologies

Abstract

The different degradation mechanisms encountered in N- and P-MOSFET's are reviewed focusing on the main processing modifications carried out in recent CMOS technologies. With the supply voltage lowering and gate-oxide thinning, a significant reduction in the amount of Hot-Carrier generation is expected while the increasing effects of charge detrapping and tunneling mechanisms will modify the reliability criterion. This will first be examined measuring the Hot-Carrier generation rate in the last CMOS technologies. Following that goal, DC and AC experiments performed in inverter- and pass transistor-configurations are studied in order to determine to what extent the effects and mechanisms are affecting the resultant degradation behavior in both device types. Based on these results, a brief outlook ends this presentation about the evolution of the Hot-Carrier problem for the next generation.