Hybrid built-in self test (BIST) for sequential circuits

Abstract

As SoC complexity continues to increase, BIST ideas are in big demand to facilitate test procedures. This helps individual blocks of memory and logic to test themselves. Unfortunately, pseudo random pattern testing methods in BIST are known to result in poor fault coverage and long test time for most sequential circuits. Employing more test vectors or using full scan could help increase the fault coverage at the expense of time and silicon area. Long test time as a result of introducing too many clock cycles is a bottleneck in test procedures. In this paper, we try to answer this problem statement. What does it take to achieve high fault coverage by sampling the results at earlier clock cycles? To answer this question, we employ the hold/release clock at test pattern generator and modified random pattern generator (MPRPG) which leads to substantial increase of fault coverage sampled at earlier clocks.