A Configurable Implementation of Adaptive Digital Predistortion System for RF Power Amplifiers

Abstract

The implementation details of an adaptive closed-loop digital predistortion (DPD) system with various configurations are presented. Convergence rate, memory depth, digital pre-distortion enable and adaptive loop enable control options are explored to increase the performance of overall DPD system in practical cases. Look-up table (LUT) based algorithm is selected and system implementation details are provided. It is shown that convergence rate is important for the speed and the stability of the DPD system. Also other control options are required to implement an efficient DPD system. The system is modeled with Matlab-Simulink and then implemented on FPGA to see the resource utilization. Based on the simulations, the system can provide more than 10dB ACPR improvement within 500 μs when the convergence rate and the memory depth are selected properly.