Electrical and thermal analysis for design exchange formats in three dimensional integrated circuits

Abstract

Three dimensional integrated circuits (3D ICs) built with through-silicon vias (TSVs) have smaller planar dimensions, shorter wire length, and better performance than 2D ICs. Many 3D stacks will combine digital and analog/RF circuitry, requiring a strong analog/mixed-signal capability. Because of the unique packaging requirements of stacked die, an IC/package co-design capability is required. Hence there must be some standards to facilitate smooth and effective design of 3D ICs. Thus the main purpose of an exchange format (EF) between dies is to permit sharing of information necessary for design by external parties without disclosing their intellectual property (IP). The requirements of the standards should be the minimum necessary to produce satisfactory answers. Producing such models is a customer support function, not a core engineering function, i.e. it is not generated by the chip design scheme. The role of the standards is to facilitate the transfer of information through a compact model, not necessarily to build one. This paper presents initial efforts in designing such standards or EF. Steady state electrical and thermal simulations are performed in this paper to demonstrate the necessary information that needs to be exchanged between the dies to ensure adequate co-design.