Yain-Reu Lin, Chia-Hao Hsu, R. Rieger, Chua-Chin Wang
{"title":"Low power RC5 cipher for ZigBee portable biomedical systems","authors":"Yain-Reu Lin, Chia-Hao Hsu, R. Rieger, Chua-Chin Wang","doi":"10.1109/ICCE.2011.5722770","DOIUrl":null,"url":null,"abstract":"This paper presents a half-run RC5 cipher architecture with low power dissipation for transmission security of biomedical systems. The proposed architecture uses a resource-sharing approach utilizing only one adder/subtractor, one bi-directional barrel shifter, and one XOR with 32-bit bus width. Therefore, two data paths are switched through four multiplexers in the encryption/decryption procedure. A prototype chip is fabricated by a standard 0.18 μm CMOS technology. The size is 704∗697 μm2, where a total of 1.64k gates are used. The proposed architecture consumes 5.87 mW@50 MHz system clock.","PeriodicalId":256368,"journal":{"name":"2011 IEEE International Conference on Consumer Electronics (ICCE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International Conference on Consumer Electronics (ICCE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCE.2011.5722770","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper presents a half-run RC5 cipher architecture with low power dissipation for transmission security of biomedical systems. The proposed architecture uses a resource-sharing approach utilizing only one adder/subtractor, one bi-directional barrel shifter, and one XOR with 32-bit bus width. Therefore, two data paths are switched through four multiplexers in the encryption/decryption procedure. A prototype chip is fabricated by a standard 0.18 μm CMOS technology. The size is 704∗697 μm2, where a total of 1.64k gates are used. The proposed architecture consumes 5.87 mW@50 MHz system clock.