Optimized design of successive approximation time-to-digital converter with single set of delay lines

Abstract

The paper addresses the problems of design of picosecond resolution time-to-digital converter based on successive approximation (SA-TDC). The principle of the conversion process in SA-TDC consists in successive delaying the events defining a start and a stop of the input time interval by the use of binary-weighted delays. The paper is focused on optimization of particular components of the SA-TDC architecture with a single set of delay lines in order to reduce differential (DNL) and integral (INL) nonlinearities. In particular, the paper contribution is an improvement of time resolution of the converter from 25 ps to 12.5 ps (i.e., by one extra bit) in 180 nm CMOS technology through enhancements of design of circuit components which results in a reduction of conversion errors.