BiNMOS: a basic cell for BiCMOS sea-of-gates

Abstract

A BiNMOS test chip has been designed and fabricated in 0.8-μm BiCMOS technology. The test chip consists of a 4×22 array of BiNMOS cells. The test structures include a ring oscillator, a 4-bit SRAM (static random-access memory) core, five types of buffers, a MUX, and a shift register. Ring oscillator measurements indicate a basic BiNMOS inverter delay of 240 ps (FO=1), a result that agrees well with simulation