A speed enhancement DRAM array architecture with embedded ECC

Abstract

A new array architecture with countermeasures for the smaller signal charge caused by scaling down is proposed. On the basis of a new access model, the combination of a hierarchical data bus configuration and multipurpose register (MPR) provides high-speed array access. The MPR also includes a practical array-embedded ECC with little area penalty and no access overhead in the page mode. This array architecture is applied to a scaled-down 16-Mbit DRAM and has achieved high performance.