A manufacturing perspective of wafer level CSP

Abstract

The micro SMD package, a wafer level Chip Scale Package (CSP), was successfully introduced by National Semiconductor about two years ago for portable wireless applications where weight, thin form factor, and board space savings are as critical as increased functionality. The package provides a matrix interconnect layout at 0.5 mm pitch, does not require underfill, and leverages standard surface mount assembly techniques. This paper will evaluate the pros and cons of packaging this wafer level CSP against a conventional leaded package and a traditional CSP.