Product-Level Reliability Estimator with advanced CMOS technology

Jae-Gyung Ahn, Ming Feng Lu, P. Yeh, J. Chang, Xin Wu, S. Pai
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引用次数: 12

Abstract

A Product-Level Reliability Estimator (PLRE), which calculates failure rate of a chip as a function of use conditions, has been developed for the first time. Major wafer-level failure mechanisms such as Time-Dependent Dielectric Breakdown (TDDB) and Electro Migration (EM) are included. By applying PLRE to the product with advanced CMOS technology, contributions from each block and each failure mechanism were quantitatively identified. It was shown that, at the target time-to-failure (TTF), gate dielectric (GD) TDDB takes the biggest portion of the failure rate, but the first failure comes with EM.
采用先进CMOS技术的产品级可靠性估计器
首次开发出了以使用条件为函数计算芯片故障率的产品级可靠性估计器(PLRE)。主要的晶圆级失效机制,如时间相关介电击穿(TDDB)和电迁移(EM)。通过将PLRE应用于具有先进CMOS技术的产品,定量地确定了每个块的贡献和每个失效机制。结果表明,在目标失效时间(TTF)下,栅极介电介质(GD) TDDB在故障率中所占的比例最大,但EM首先发生失效。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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