Exploiting parallelism to speed up circuit legalization

Abstract

During physical synthesis, global placement produces a solution where cells are overlapped or misaligned with respect to circuit sites and rows. Therefore, a legalization step relocates a subset of cells in order to satisfy a set of legality constraints. Although several techniques have been proposed to solve the legalization problem, they were designed without considering parallelization. This work investigates the speedup that can be achieved by parallelizing full circuit legalization. For such evaluation we implemented a parallel version of the Abacus algorithm. Experimental results show that the proposed implementation achieves up to 2.43 times speedup with the same solution quality.