Test and configuration architecture of a sub-THz CMOS detector array

Abstract

This paper describes the architecture and testability issues of a 90 nm CMOS sub-THz detector array ASIC. The sub-THz detector array is an integrated system composed of silicon field effect plasma wave sensors, integrated antennas, pre-amplifiers, ADCs, and digital domain lock-in amplifier detector. The mixed-signal system is controlled and monitored by JTAG interface containing several access points and multiple power domains. The peak responsivity is found 185 kV/W@365 GHz and at the detectivity maximum the NEP ~ 20 pW/Hz-1.