Parasitic conduction in a 0.13 /spl mu/m CMOS technology at low temperature

Abstract

Low temperature measurements at 4.2 K and 77 K are performed on n- and p-MOSFETs of a 0.13 μm CMOS technology. Two parasitic current contributions are identified in the subthreshold regime and strong inversion at 4.2 K. The first one is related to a parasitic parallel conduction inherent to Shallow Trench Isolation. Whereas the second one, resulting in a second peak in the linear transconductance, is discussed in terms of a stronger impact of substrate majority carriers due to a higher substrate resistivity at 4.2K. The measured substrate current in n-MOSFETs is probably originating from electrons tunneling from the substrate valence band to the gate. At 4.2 K, the substrate current induces a reduction of the threshold voltage resulting in the measured kink of the b(V G ) characteristic and the second transconductance peak at low drain bias.