An efficient architecture of one chip network processor for IEC 61850

Abstract

In this paper, an efficient architecture of IEC 61850 network processor is proposed. Proposed architecture can achieve the low power consumption and the high reliability by the dedicated communication stack of IEC 61850 that implemented with HDL. And minimized control signal between main and IEC 61850 stack processor could help to increase the reliability and the processing speed. The proposed architecture implemented with Verilog HDL and verified with the test board. The proposed one chip solution process the advantage of low cost, low power, reliability and can be used for developing devices based on IEC 61850.