{"title":"Low power high bandwidth amplifier with RC Miller and gain enhanced feedforward compensation","authors":"Shagun Bajoria, V. Singh, Raju Kunde, C. Parikh","doi":"10.1145/1393921.1393972","DOIUrl":null,"url":null,"abstract":"An improved frequency compensation technique is presented for low-power low-voltage three-stage operational amplifiers with high capacitive loads. The technique uses single RC Miller compensation and a direct gain enhanced feedforward path from the input to the output. With a load capacitance of 300 pF, the amplifier nominally achieves a dc gain of 74 dB, a 3-dB bandwidth of 2.9 kHz, a 52 degrees phase margin, and a slew rate of 0.22 V/μs, while consuming 0.24 mW of power with a 1.2-V supply voltage, in a 180 nm CMOS technology. The 3-dB bandwidth is one of the highest reported for a high-gain three-stage CMOS amplifier.","PeriodicalId":166672,"journal":{"name":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceeding of the 13th international symposium on Low power electronics and design (ISLPED '08)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1393921.1393972","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
An improved frequency compensation technique is presented for low-power low-voltage three-stage operational amplifiers with high capacitive loads. The technique uses single RC Miller compensation and a direct gain enhanced feedforward path from the input to the output. With a load capacitance of 300 pF, the amplifier nominally achieves a dc gain of 74 dB, a 3-dB bandwidth of 2.9 kHz, a 52 degrees phase margin, and a slew rate of 0.22 V/μs, while consuming 0.24 mW of power with a 1.2-V supply voltage, in a 180 nm CMOS technology. The 3-dB bandwidth is one of the highest reported for a high-gain three-stage CMOS amplifier.