A system for asynchronous high-speed chip to chip communication

Abstract

A system for high-speed asynchronous interconnections between VLSI chips is proposed. Communication is performed on three-wire links that have about the same properties as differential interconnections. A bit transmission consists of switching the constant driver current from one wire to one of the two others. There is no need for clocking or synchronisation, as bits are separated by a transition. The chosen data representation makes decoding to a two-phase protocol especially simple. Energy consumption may be reduced by dynamically adjusting bias currents, and thus circuit speed, to match the demand for communication bandwidth. In a 0.7 /spl mu/m CMOS process, communication bandwidth per link is expected to reach 1 Gb/s.