Automatic design of low power CMOS buffer-chain circuit using differential evolutionary algorithm and particle swarm optimization

Abstract

PSO and DE algorithms and its variants are used for the optimization of a buffer-chain circuit and the results of all the algorithms are compared in this literature. By testing these algorithms on different mathematical benchmark functions the best parameter values of buffer chain circuit are obtained in such a way that it reduces the error between simulated output and optimized output, hence giving the best circuit performance. Evolutionary algorithms are better in performance and speed than the classical methods. 130nm CMOS technology has been used in this work. With the help of these parameter values the circuit simulator gives the values of power consumption, symmetry, rise time and fall time, which are almost closer to the desired specification of the buffer chain circuit.