A 3.2-to-3.8GHz Calibration-Free Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving –66dBc Worst-Case In-Band Fractional Spur

Abstract

A dual-feedback architecture for a fractional-N PLL is proposed to achieve low spurs and to suppress the phase noise degradation from the Delta-Sigma Modulator (DSM). With the assistance of 1 auxiliary PLL, the proposed architecture avoids noise amplification that occurs in conventional architectures. The feasibility of the proposed architecture is demonstrated in a calibration-free 3.2-to-3.8GHz analog fractional-N PLL that achieves –69dBc out-of-band spur and –66dBc worst-case in-band fractional spur.