D. Sawdai, P. C. Chang, Vincent Gambin, X. Zeng, J. Yamamoto, K. Loi, G. Leslie, Michael E. Barsky, A. Gutierrez-Aitken, A. Oki
{"title":"Planarized InP/InGaAs heterojunction bipolar transistors with f/sub MAX/ > 500 GHz","authors":"D. Sawdai, P. C. Chang, Vincent Gambin, X. Zeng, J. Yamamoto, K. Loi, G. Leslie, Michael E. Barsky, A. Gutierrez-Aitken, A. Oki","doi":"10.1109/DRC.2004.1367903","DOIUrl":null,"url":null,"abstract":"To meet the demands for next generation high-speed electronics, the InP-based heterojunction bipolar transistor (HBT) must be scaled vertically to minimize transit times, scaled laterally to minimize the emitter width (W/sub E/) and the base-collector junction capacitance (C/sub BC/), and fabricated with high yield to support large circuits. Lateral scaling can involve a variety of processing techniques. In this work, we developed a dielectric planarization process which enabled aggressive scaling of both W/sub E/ and C/sub BC/ using production I-line lithography, resulting in emitters as small as 0.14 /spl mu/m, unity gain cutoff frequency (f/sub T/) up to 290 GHz, and maximum oscillation frequency (f/sub MAX/) greater than 500 GHz.","PeriodicalId":385948,"journal":{"name":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","volume":"64 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2004.1367903","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
To meet the demands for next generation high-speed electronics, the InP-based heterojunction bipolar transistor (HBT) must be scaled vertically to minimize transit times, scaled laterally to minimize the emitter width (W/sub E/) and the base-collector junction capacitance (C/sub BC/), and fabricated with high yield to support large circuits. Lateral scaling can involve a variety of processing techniques. In this work, we developed a dielectric planarization process which enabled aggressive scaling of both W/sub E/ and C/sub BC/ using production I-line lithography, resulting in emitters as small as 0.14 /spl mu/m, unity gain cutoff frequency (f/sub T/) up to 290 GHz, and maximum oscillation frequency (f/sub MAX/) greater than 500 GHz.