Power line communication chip design with data error detecting/correcting and data encrypting/decrypting ability

Abstract

This paper presents a low cost chip design of Power Line Communication for the applications in the home networks. The data transmission occur burst errors easily by the noise interference from the environment. In order to reduce the error rate, an all-digital modulation/demodulation chip with error correctable and high error detected ability for power line communication is designed. The proposed design consists of Cyclic Redundancy Check, Digital Pulse Width Modulation, Digital Frequency Shift Keying, Forward Error Correction, interleaving techniques, and Tiny Encryption Algorithm. The fabricated chip area is 1.352 mm2 with 3.3/1.8 supply voltages. The measured data shows that the proposed design is fully functional and consumes 70 μW.