Jidan Al-Eryani, H. Knapp, J. Wursthorn, K. Aufinger, S. Majied, Hao Li, S. Boguth, R. Lachner, J. Bock, L. Maurer
{"title":"A 162 GHz power amplifier with 14 dBm output power","authors":"Jidan Al-Eryani, H. Knapp, J. Wursthorn, K. Aufinger, S. Majied, Hao Li, S. Boguth, R. Lachner, J. Bock, L. Maurer","doi":"10.1109/BCTM.2016.7738965","DOIUrl":null,"url":null,"abstract":"A 3-stage power amplifier (PA) with 14dBm saturated output power (Psat), 29.5 dB small-signal gain, and 4.8% power-added efficiency (PAE) at a frequency of 162GHz is presented. From 155 to 165 GHz, Psat remains higher than 12.5 dBm, while the small-signal gain varies from 35.4 dB to 28.3 dB. Maximum output power and gain performance are obtained by using a differential cascode topology and operating the transistors well beyond their open-base collector-emitter breakdown voltage (BVCEO), and by optimum matching of the three stages of the PA. To our best knowledge, this is the highest reported output power for a sillicon-based PA beyond 150 GHz. The chip is fabricated in a 130nm SiGe BiCMOS technology with fT/fmax = 250/370 GHz.","PeriodicalId":431327,"journal":{"name":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BCTM.2016.7738965","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 17
Abstract
A 3-stage power amplifier (PA) with 14dBm saturated output power (Psat), 29.5 dB small-signal gain, and 4.8% power-added efficiency (PAE) at a frequency of 162GHz is presented. From 155 to 165 GHz, Psat remains higher than 12.5 dBm, while the small-signal gain varies from 35.4 dB to 28.3 dB. Maximum output power and gain performance are obtained by using a differential cascode topology and operating the transistors well beyond their open-base collector-emitter breakdown voltage (BVCEO), and by optimum matching of the three stages of the PA. To our best knowledge, this is the highest reported output power for a sillicon-based PA beyond 150 GHz. The chip is fabricated in a 130nm SiGe BiCMOS technology with fT/fmax = 250/370 GHz.