Interfacial layer dependence of High-K gate stack based Conventional trigate FinFET concerning analog/RF performance

Abstract

In this paper, the effect of interfacial layer thickness (TI) on the analog/RF performance of high-$k$ gate-stack based conventional trigate FinFET has been studied. It is found that the deterioration in analog/RF performance caused by high-$K$ gate dielectrics may be mitigated by using a thicker interfacial layer of silicon dioxide. The deterioration in intrinsic dc gain $(\Delta \mathrm{Av}== \mathrm{Av}_{(\mathrm{k}=3.9)} - \mathrm{Av}_{(\mathrm{k}=40)})$ and cut-off frequency $(\Delta \mathrm{f_{T}} = \mathrm{f_{T(K=3.9)}} - \mathrm{f_{T(K=40)})}$ is 7.14 dB & 13.4 GHz respectively for interfacial layer thickness of 0.2 nm and 2.27 dB & 8.7 GHz respectively for interfacial layer thickness of 0.7 nm. Thus, usage of high-$K$ gate dielectric with thicker interfacial layer is more beneficial in trigate FinFET devices for better analog/RF performance.