Floating-Point FIR-Based Convolution Suitable for Discrete Wavelet Transform Implementation on FPGA

Abstract

In this paper, the FPGA implementation of the convolution block suitable for Discrete Wavelet Transform (DWT) decomposition is presented. The transposed form Finite Impulse Response (FIR) structure is employed for performing the convolution process. The design is generic in nature to fit for different wavelet types and symmetric to expand for filters of multiple taps. The proposed convolution block is integrated to design a DWT decomposition system as an application. the proposed architecture is implemented using IEEE -754 single precision floating-point representation offering higher precision and better accuracy than scaled integer wavelet coefficients. The whole system is implemented on Virtex 5 FPGA achieving 243.6 MHz clock frequency.