Fault tolerance: a verification strategy for switching systems

Abstract

At GLOBECOM 87, R. Paterson described the new approach to performing failure mode analysis. This technique insured that each high-level functional failure mode of the detailed design is detected, recovered, and isolated according to the intent of the system-level design. Since that work, Bell-Northern Research has improved the technique and developed a toolset to make the analysis more efficient and effective. The toolset models a system from the high-level architecture to the device level while taking the software maintenance design into consideration. The model calculates the impact of subtle detail design changes at the system level and consequently identifies the effect on the end user and the operating company. The BNR design process and fault-tolerant verification process are described. To illustrate the approach considered, a switching network for a telephone switch is considered. It is concluded that the current fault tolerant verification strategy with the complementing toolset is an effective and efficient way of designing high-quality fault-tolerant systems.<>