Real-time integer convolution implemented using systolic arrays and a digit-serial architecture in complex programmable logic devices

Abstract

In this work an FIR filter is designed, combining the systolic architecture with the digit-serial technique. Multipliers are designed with this technique and the accumulator exploits these characteristics avoiding the lack of real-time computing capability and data processing speed. The system can be used in realtime digital signal and image processing applications. The simulation results presented were obtained using the FLEX 10K20 device of Altera.