Asynchronous logical system simulation in VHDL

Abstract

The following article describes the fundamentals of asynchronous logical systems from handshaking protocols to Muller pipeline. Understanding these fundamentals is important to analysing problems. The aim of this article is to solve problems with the design and simulation of asynchronous circuits. The final results are simulation models of a 4-phase bundled-data pipeline and a 4-phase dual-rail pipeline. The simulation models were generated in the simulation tool Modelsim with real gate delays and with zero wire delays.