Experiments in detecting delay faults using multiple higher frequency clocks and results from neighboring die

Abstract

This paper presents experimental results from circuits specially implemented to evaluate a new technique for detecting delay faults in scan based designs. The faults are detected by observing circuit outputs at multiple capture intervals, each progressively shorter than the nominal switching delay for the logic block. For this study a simple datapath circuit was designed and fabricated through MOSIS. Extra capacitive delays were deliberately introduced in a copy of the design. The test results presented here clearly establish the signGCant potential of the proposed new delay testing approach.