Recent advances in low temperature process in view of 3D VLSI integration

2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) Pub Date : 2016-10-01 DOI:10.1109/S3S.2016.7804404

C. Fenouillet-Béranger, P. Batude, L. Brunet, V. Mazzocchi, C-M. V. Lu, F. Deprat, J. Micout, M.-P. Samson, B. Previtali, P. Besombes, N. Rambal, V. Lapras, F. Andrieu, O. Billoint, M. Brocard, S. Thuries, G. Cibrario, P. Acosta-Alba, B. Mathieu, S. Kerdilès, F. Nemouchi, C. Arvet, P. Besson, V. Loup, R. Gassilloud, X. Garros, C. Leroux, V. Beugin, C. Guérin, D. Benoit, L. Pasini, J. Hartmann, M. Vinet

引用次数: 11

Abstract

In this paper, the recent advances in low temperature process in view of 3D VLSI integration are reviewed. Thanks to the optimization of each low temperature process modules (dopant activation, gate stack, epitaxy, spacer deposition) and silicide stability improvement, the top layer thermal budget fabrication has been decreased in order to satisfy the requirements for 3D VLSI integration.

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三维VLSI集成低温工艺研究进展

本文从三维VLSI集成的角度，综述了低温工艺的最新进展。由于优化了每个低温工艺模块(掺杂激活、栅极堆叠、外延、间隔层沉积)和硅化物稳定性，减少了顶层热预算制造，以满足3D VLSI集成的要求。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

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