Experiments in sub-micron CMOS technology: the JISI project

E. Sicard, J. Huang, J. Fourniols, A. Ferreira, J. Noullet
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Abstract

This paper describes a set of micro-electronics experiments implemented in a 0.7 /spl mu/m CMOS integrated circuit used for the training of graduate students. A set of 10 experiments are implemented on the chip and include basic devices such as MOS transistors, diodes, and silicon sensors, as well as design oriented experiments (complex gates, latches) and analog experiments (operational amplifiers, crosstalk sensors, voltage controlled oscillators). The chip, named JISI has been fabricated in various CMOS technologies for performance evaluation with the technology scaling down.
亚微米CMOS技术实验:JISI项目
本文介绍了一套在0.7 /spl μ m CMOS集成电路上实现的用于研究生培养的微电子学实验。在该芯片上实现了一组10个实验,包括MOS晶体管、二极管和硅传感器等基本器件,以及面向设计的实验(复杂门、锁存器)和模拟实验(运算放大器、串扰传感器、压控振荡器)。该芯片名为JISI,已在各种CMOS技术中制造,用于性能评估。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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