High Speed Buried Channel In0.53Ga0.47As/InP MOSFET with Corner Spacer for Low Power Applications

Abstract

In the nanoscale regime circuit and device performance degrades due to the presence of parasitic capacitance. In the case of scaled devices, short channel effects (SCEs) are substantially reduced by using gate underlap at source and drain side with a significant reduction of drain current. Again, the implementation of the spacer on either side of the gate region helps to realize better drain current with a substantial increase in parasitic capacitance (Cgg), which deteriorates the device performance. In order to overcome these drawbacks, a corner spacer (CS) is introduced in double gate heterostructure MOSFET (DG-HMOSFET), which improves the device characteristics with the reduction in parasitic capacitances. The proposed work presents the comparison among spacer (S) and CS on DG-HMOSFET in order to realize the improvement of device parameters. Thus, the incorporation of high-k on CS- DG-HMOSFET shows the reduction in parasitic capacitance in all directions as compared to S-DG-HMOSFET.