Enhanced techniques for current balanced logic in mixed-signal ICs

Abstract

In this paper, dual-V/sub T/ and negative feedback are proposed to reduce the noise of the current-balanced logic for mixed-signal ICs. Based on the circuit analysis and SPICE simulation, the dual-V/sub T/ technique shows advantages over the conventional current-balanced logic design in gate area, delay, power dissipation, and switching noise. The negative feedback further reduces the noise spike.