Characterization and analysis of a new gate leakage mechanism at high drain bias in InAlAs/InGaAs heterostructure field-effect transistors

Abstract

InAlAs/InGaAs Heterostructure Field-Effect Transistors (HFET) exhibit excellent DC- and RF- performance and are well suited for low power applications in the millimeter-wavelength range. Using sophisticated crystal growth modes and device fabrication techniques, the capability of high power applications was also demonstrated. But with increasing drain-source voltages V/sub ds/>3 V it new parasitic phenomenon can be detected additive to the well-known gate leakage mechanism. An exponentially growing gate current bump, strongly dependent on the HFET design, appears at positive gate-source voltages V/sub gs/.