NMOS/NLDMOS LSS dead-time minority carrier isolation optimization

Abstract

NMOS/NLDMOS LSS dead-time minority carrier isolation is critical for Synchronous Step-down converter products both for reliability and die size cost. We evaluate MAAP isolation ring design effectiveness using TCAD simulation with 1, 10 and 100uA/um dead-time currents. Instead of using a simple diode as injection source, we took a wholistic approach to include the LSS NMOS or NLDMOS in the test structures. Transient simulation results show that instead of body diode, MOS channels conduct most of the current. This is verified by NMOS and NLDMOS transistor silicon material measurements. With the low level of actual body diode current and substrate electron injection, we found there is a lot of room to achieve high performance minority carrier isolation and significant die size cost reduction on the isolation ring region at the same time.