SiGe HBTs with ${f_{T}/f_{\max}\,\sim\,375/510GHz}$ Integrated in 45nm PDSOI CMOS

J. Pekarik, V. Jain, C. Kenney, J. Holt, S. Khokale, S. Saroop, Jeffrey B. Johnson, K. Stein, V. Ontalus, Christopher Durcan, Mona Nafari, T. Nesheiwat, S. Saudari, Elahe Yarmoghaddam, Saloni Chaurasia, A. Joseph
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Abstract

A 45nm BiCMOS process, based on PDSOI CMOS, with SiGe HBT NPNs having ${f_{T}f_{\max}\,=\,375/510GHz}$ is presented. The bipolars are integrated on a PDSOI wafer in an epitaxial region above the handle wafer to avoid self-heating concerns. To our knowledge, this is the first time a high performance SiGe BiCMOS process has been demonstrated on a PDSOI wafer. In addition to the HBTs, the technology features high performance NFETs with ${f_{T}f_{MAX}\,=\,265/330GHz}$ and PFETs with ${f_{T}f_{MAX}\,=\,250/340GHz}$ enabling flexibility in circuit design. A full-flow demonstration PDK, digital standard cell and IO cell libraries have been released for experimental circuit design work. This work, funded under the DARPA T-MUSIC program, will address future extensions to higher HBT performance and more-advanced CMOS nodes.
SiGe HBTs与${f_{T}/f_{\max}\,\sim\,375/510GHz}$集成在45nm PDSOI CMOS
提出了一种基于PDSOI CMOS的45nm BiCMOS工艺,其SiGe HBT NPNs为${f_{T}f_{\max}\,=\,375/510GHz}$。双极集成在PDSOI晶圆上,位于手柄晶圆上方的外延区域,以避免自热问题。据我们所知,这是第一次在PDSOI晶圆上展示高性能SiGe BiCMOS工艺。除hbt外,该技术还具有${f_{T}f_{MAX}\,=\,265/330GHz}$的高性能nfet和${f_{T}f_{MAX}\,=\,250/340GHz}$的pfet,可实现电路设计的灵活性。一个完整的演示PDK、数字标准单元和IO单元库已经发布,用于实验电路设计工作。这项工作由DARPA T-MUSIC项目资助,将解决未来更高HBT性能和更先进CMOS节点的扩展问题。
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