FPGA implementation of hybrid Han-Carlson adder

Abstract

In this paper a modified parallel prefix adder, Hybrid Han-Carlson adder is proposed which uses different stages of Brent-Kung and Kogge-Stone adders. Binary addition is one of the primitive and most commonly used application in computer arithmetic. Parallel prefix adders offer a highly efficient solution to the binary addition problem and are well suited for FPGA implementation. Carry propagation in binary addition can be efficiently expressed as a prefix computation. Modified Hybrid Han-Carlson adder reduces the complexity, area and power consumption significantly.