Security through obscurity: Integrated circuit obfuscation using don't care conditions

Abstract

Obfuscation has emerged as a promising approach to ensure supply chain security by countering the reverse engineering (RE) based attacks on integrated circuits that violate intellectual property rights of the circuit designer. However, current obfuscation methods either rely on secure memory to store the key or incur large design overhead with camouflaged gates. We propose a set of don't care based obfuscation primitives and show how they can be used to make the design IP secure with little area and delay overhead. While existing logic obfuscation techniques rely on hiding layout information from circuit attackers, our approach is different in that we introduce confusion in the sub-circuit functionality in order to increase the RE complexity while meeting the overall circuit specification. We also study how to maximize the complexity of the RE attacks and incorporate the conclusion of such a study into the proposed don't care based obfuscation method. Simulation results for ISCAS-85 benchmarks confirm that we can achieve circuit obfuscation with very high RE complexity and small design overhead, more specifically, an average 7.73% delay overhead and 5.51% area overhead.