Minimizationof wirelength in 3d IC routing by using differential evolution algorithm

Abstract

The wire-length of vertically stacked ICs plays a vital role. The wire-length is minimized by using differential evolutionary algorithms withIBM Benchmark inputs. Moreover this wire length is minimized with the respect to the length of the Through Silicon via (TSVs). As a result, the wire-length has been minimized using this algorithm with various parameters. Experimental result shows that the total wirelength can be reduced.