Characterization and high speed digital application of GaAs MESFETs on Si substrates

Abstract

Summary form only given. The authors optimized the device structure to suppress the short channel effect due to the residual stress in GaAs/Si substrates and improved the microscopic uniformity. The residual-stress problem was solved by introducing a p-layer (C/sup +/: 140 keV) buried under the n-type channel (Si/sup +/: 20 keV) in the n/sup +/ self-alignment technique with refractory W-Al gate. The authors then evaluated the microscopic uniformity of the device on GaAs/Si using 60- mu m*60- mu m-pitch FET arrays, and found that it is improved by introducing the p-layer. To evaluate the dynamic characteristics, a direct-coupled FET logic (DCFL) ring oscillator was fabricated using a 0.3- mu m-gate MESFET on the GaAs/Si substrate. The propagation delay was as small as 19.9 ps/gate at a supply voltage of 2 V. >