8912-bit Montgomery multipliers using radix-8 booth encoding and coded-digit

Abstract

This paper presents the design of 8192-bit Montgomery multipliers based on radix-8 Booth encoding and coded-digit. Both multipliers use a systolic architecture and simultaneously carry out two multiplications. The designs are described in generic structural VHDL, synthesized on the EP4SGX230KF40C2 using Quartus II V.12, and verified using SignalTap. The hardware synthesis and performance results show that the designed multipliers present a good area-throughput trade-off and they are suitable for use into a hardware cryptoprocessor.