On the FPGA board level routing problem

Conference Proceedings. IEEE Canadian Conference on Electrical and Computer Engineering (Cat. No.98TH8341) Pub Date : 1998-05-24 DOI:10.1109/CCECE.1998.682778

Xiaoyu Song, Yuke Wang

引用次数: 1

Abstract

We study a two-terminal board level routing problem applicable to FPGA-based logic emulation systems. The problem was studied by W. Mak and D.F. Wong (see IEEE Trans. CAD, vol.16, no.3, 1997), where an algorithm of O(n/sup 2/) time was proposed, where n is the number of nets. We present a new and simple O(n)-time routing algorithm for solving the problem. A new precise I/O capacity constraint for routability is given by taking other criteria (e.g., the number of chips) into consideration.

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关于FPGA板级路由问题

研究了一种适用于fpga逻辑仿真系统的双端板级路由问题。这个问题是由W. Mak和D.F. Wong研究的。CAD, vol.16, no。3, 1997)，其中提出了O(n/sup 2/)时间的算法，其中n为网数。我们提出了一种新的简单的O(n)时间路由算法来解决这一问题。考虑到其他标准(如芯片数量)，给出了一种新的精确的I/O容量约束。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Conference Proceedings. IEEE Canadian Conference on Electrical and Computer Engineering (Cat. No.98TH8341)

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