Fully integrated serial-link receiver with optical interface for long-haul display interconnects

Kang-Yeob Park, W. Oh, Y. Lee, W. Choi
{"title":"Fully integrated serial-link receiver with optical interface for long-haul display interconnects","authors":"Kang-Yeob Park, W. Oh, Y. Lee, W. Choi","doi":"10.1049/iet-cds.2012.0029","DOIUrl":null,"url":null,"abstract":"We report a fully integrated serial-link receiver with optical interface fabricated with a 0.18 µm complementary metal oxide semiconductor technology for long-haul display interconnects. The receiver includes a trans-impedance amplifier, a limiting amplifier, a clock and data recovery circuit, 1:64 de-multiplexer and a built-in error checker. The receiver produces 64-bit wide electrical signals from photodetector output signals produced by 5.28, 5.6 or 6.25 Gb/s optical signals delivered through up to 700-m multi-mode fibre. It can support serialised data for Ultra eXtended Graphics Array (UXGA), 1080 p and Wide Ultra eXtended Graphics Array (WUXGA). The receiver core occupies 0.59 mm2 with 42.4 mW power dissipation at 6.25 Gb/s bit rate from a 1.8 V supply.","PeriodicalId":120076,"journal":{"name":"IET Circuits Devices Syst.","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2012-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IET Circuits Devices Syst.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1049/iet-cds.2012.0029","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1

Abstract

We report a fully integrated serial-link receiver with optical interface fabricated with a 0.18 µm complementary metal oxide semiconductor technology for long-haul display interconnects. The receiver includes a trans-impedance amplifier, a limiting amplifier, a clock and data recovery circuit, 1:64 de-multiplexer and a built-in error checker. The receiver produces 64-bit wide electrical signals from photodetector output signals produced by 5.28, 5.6 or 6.25 Gb/s optical signals delivered through up to 700-m multi-mode fibre. It can support serialised data for Ultra eXtended Graphics Array (UXGA), 1080 p and Wide Ultra eXtended Graphics Array (WUXGA). The receiver core occupies 0.59 mm2 with 42.4 mW power dissipation at 6.25 Gb/s bit rate from a 1.8 V supply.
完全集成的串行链路接收器与光学接口,用于长途显示互连
我们报告了一种完全集成的串行链路接收器,其光接口采用0.18 μ m互补金属氧化物半导体技术制造,用于长距离显示互连。接收机包括一个反阻抗放大器、一个限幅放大器、一个时钟和数据恢复电路、1:64解复用器和一个内置错误检查器。接收器从光电探测器输出的5.28、5.6或6.25 Gb/s光信号中产生64位宽电信号,这些光信号通过长达700米的多模光纤传输。它可以支持超扩展图形阵列(UXGA), 1080p和宽超扩展图形阵列(WUXGA)的序列化数据。在1.8 V电源下,在6.25 Gb/s比特率下,接收器核心占地0.59 mm2,功耗42.4 mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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