Low-Power 13-Bit DAC with a Novel Architecture in SA-ADC

Abstract

A novel capacitive digital to analog convertor (DAC) is presented, suitable for low-power data conversion applications like portable stuffs as well. A 5-bit resistor string decreases the capacitor sizes and consequently the power consumption and the chip die size. The idea is applied to a 13-bit successive approximation analog to digital convertor (SA-ADC) where the bottom plate sampling and holding is performed in the same capacitors of the DAC. Moreover, no return to zero occurs during the quantization procedure. All these advantages reduce the power consumption more and more where the simulation results through HSPICE software level 49 parameters in $\pmb{0.18\mu \mathrm{m}}$ standard CMOS process prove the precise operation and the great improvements. The proposed SA-ADC works with 1.8V power supply and it has the power consumption of $\pmb{100\mu \mathrm{W}}$.