Design and implementation of a hybrid switching router for the reconfigurable Network-on-Chip

Abstract

Network-on-Chip (NoC) has been proposed as the communication paradigm for the Ultra Large-Scale Integration System-on-Chips. One of the key factors that determine the performance and the implementation cost of a NoC is the switching scheme. In this paper, we propose and implement a hybrid switching router based on the combination of wormhole and virtual cut-through switching schemes. The router is dynamically reconfigurable to exchange between switching schemes at run-time, therefore, it achieves higher average performance than wormhole switching, while reducing the implementation cost in comparison with the virtual cut-through switching. The router has been modelled at Register Transfer Level in VHDL language and then synthesized on Xilinx Virtex-7 FPGA technology. The experimental results show that this router can guarantee reliability and reduce latency about 30.2% and increase average throughput approximately 38.9% compared with the generic router. The area and power overhead compared with the generic router are acceptable.